Origin of Power Converters
Decoding, Synthesizing, and Modeling
1. Auflage April 2020
416 Seiten, Hardcover
Wiley & Sons Ltd
ISBN:
978-1-119-63298-6
John Wiley & Sons
Weitere Versionen
A comprehensive guide to approaches to decoding, synthesizing and modeling pulse width modulation (PWM) converters
Origin of Power Converters explores the original converter and provides a systematic examination of the development and modeling of power converters based on decoding and synthesizing approaches. The authors--noted experts on the topic--present an introduction to the origins of the converter and detail the fundamentals related to power the converter's evolution. They cover a range of converter synthesis approaches, synthesis of multi-stage/multi-level converters, extension of hard-switching converters to soft-switching ones, and determination of switch-voltage stresses in the converters.
In later chapters, this comprehensive resource reviews conventional two-port network theory and the state-space averaged (SSA) modeling approach, from which systematic modeling approaches are based on the graft switch technique. In addition, the book reviews the converter layer scheme and some fundamental circuit theories. This important book:
* Contains a review of several typical transfer codes, such as step-down, step-up, step-up&-down, and ± step-up&-down
* Describes the syntheses of pulse width modulation (PWM) converters such as voltage-fed z-source, current-fed z-source, quasi z-source, switched capacitor, and switched inductor converters
* Presents two application examples based on previously proposed modeling approaches
Written for academic researchers, graduate students, and seniors in power electronics, Origin of Power Converters provides a comprehensive understanding of the evolution of the converter and its applications.
Preface xv
Acknowledgments xvii
About the Authors xviii
Part I Decoding and Synthesizing 1
1 Introduction 3
1.1 Power Processing Systems 4
1.2 Non-PWM Converters Versus PWM Converters 7
1.2.1 Non-PWM Converters 7
1.2.2 PWM Power Converters 9
1.3 Well-Known PWM Converters 10
1.4 Approaches to Converter Development 17
1.5 Evolution 25
1.6 About the Text 26
1.6.1 Part I: Decoding and Synthesizing 26
1.6.2 Part II: Modeling and Applications 28
Further Reading 28
2 Discovery of Original Converter 31
2.1 Creation of Original Converter 31
2.1.1 Source-Load Approach 32
2.1.2 Proton-Neutron-Meson Analogy 32
2.1.3 Resonance Approach 33
2.2 Fundamental PWM Converters 34
2.2.1 Voltage Transfer Ratios 35
2.2.2 CCM Operation 36
2.2.3 DCM Operation 38
2.2.4 Inverse Operation 39
2.3 Duality 40
Further Reading 41
3 Fundamentals 43
3.1 DC Voltage and Current Offsetting 43
3.1.1 DC Voltage Offsetting 44
3.1.2 DC Current Offsetting 47
3.2 Capacitor and Inductor Splitting 49
3.3 DC-Voltage Blocking and Pulsating-Voltage Filtering 51
3.4 Magnetic Coupling 55
3.5 DC Transformer 58
3.6 Switch Grafting 62
3.7 Diode Grafting 67
3.8 Layer Scheme 72
Further Reading 74
4 Decoding Process 77
4.1 Transfer Ratios (Codes) 77
4.2 Transfer Code Configurations 82
4.2.1 Cascade Configuration 82
4.2.2 Feedback Configuration 82
4.2.3 Feedforward Configuration 83
4.2.4 Parallel Configuration 85
4.3 Decoding Approaches 86
4.3.1 Factorization 86
4.3.2 Long Division 88
4.3.3 Cross Multiplication 89
4.4 Decoding of Transfer Codes with Multivariables 91
4.5 Decoding with Component-Interconnected Expression 93
Further Reading 94
5 Synthesizing Process with Graft Scheme 95
5.1 Cell Approaches 95
5.1.1 P-Cell and N-Cell 96
5.1.2 Tee Canonical Cell and Pi Canonical Cell 97
5.1.3 Switched-Capacitor Cell and Switched-Inductor Cell 98
5.1.4 Inductor-Capacitor Component Cells 100
5.2 Converter Grafting Scheme 101
5.2.1 Synchronous Switch Operation 101
5.2.2 Grafting Active Switches 103
5.2.3 Grafting Passive Switches 108
5.3 Illustration of Grafting Converters 110
5.3.1 Grafting the Well-Known PWM Converters 110
5.3.1.1 Graft Boost on Buck 111
5.3.1.2 Graft Buck on Boost 112
5.3.1.3 Graft Buck on Buck-Boost 114
5.3.1.4 Graft Boost on Boost-Buck 116
5.3.1.5 Buck in Parallel with Buck-Boost 119
5.3.1.6 Grafting Buck on Buck to Achieve High Step-Down Voltage Conversion 119
5.3.1.7 Grafting Boost on Boost to Achieve High Step-up Voltage Conversion 120
5.3.1.8 Grafting Boost (CCM) on Buck (DCM) 121
5.3.1.9 Cascode Complementary Zeta with Buck 123
5.3.2 Grafting Various Types of Converters 124
5.3.2.1 Grafting Half-Bridge Resonant Inverter on Dither Boost Converter 124
5.3.2.2 Grafting Half-Bridge Resonant Inverter on Bidirectional Flyback Converter 124
5.3.2.3 Grafting Class-E Converter on Boost Converter 125
5.3.3 Integrating Converters with Active and Passive Grafted Switches 127
5.3.3.1 Grafting Buck on Boost with Grafted Diode 128
5.3.3.2 Grafting Half-Bridge Inverter on Interleaved Boost Converters in DCM 128
5.3.3.3 Grafting N-Converters with TGS 130
5.3.3.4 Grafting N-Converters with PiGS 130
Further Reading 132
6 Synthesizing Process with Layer Scheme 133
6.1 Converter Layering Scheme 133
6.2 Illustration of Layering Converters 135
6.2.1 Buck Family 135
6.2.2 Boost Family 138
6.2.3 Other Converter Examples 142
6.3 Discussion 146
6.3.1 Deduction from uk to Buck-Boost 146
6.3.2 Deduction from Sepic to Buck-Boost 148
6.3.3 Deduction from Zeta to Buck-Boost 149
6.3.4 Deduction from Sepic to Zeta 150
Further Reading 151
7 Converter Derivation with the Fundamentals 153
7.1 Derivation of Buck Converter 153
7.1.1 Synthesizing with Buck-Boost Converter 154
7.1.2 Synthesizing with uk Converter 154
7.2 Derivation of z-Source Converters 154
7.2.1 Voltage-Fed z-Source Converters 155
7.2.1.1 Synthesizing with Sepic Converter 157
7.2.1.2 Synthesizing with Zeta Converter 160
7.2.2 Current-Fed z-Source Converters 161
7.2.2.1 Synthesizing with SEPIC Converter 162
7.2.2.2 Synthesizing with Zeta Converter 162
7.2.3 Quasi-z-Source Converter 162
7.2.3.1 Synthesizing with Sepic Converter 164
7.2.3.2 Synthesizing with Zeta Converter 165
7.3 Derivation of Converters with Switched Inductor or Switched Capacitor 166
7.3.1 Switched-Inductor Converters 167
7.3.1.1 High Step-Down Converter with Transfer Code D/(2 . D) 167
7.3.1.2 High Step-Down Converter with Transfer Code D/(2(1 . D)) 173
7.3.2 Switched-Capacitor Converters 178
7.3.2.1 High Step-Up Converter with Transfer Code (1 + D)/(1 . D) 178
7.3.2.2 High Step-Up Converter with Transfer Code 2D/(1 . D) 181
7.3.2.3 High Step-Up Converter with Transfer Code D/(1 . 2D) 184
7.4 Syntheses of Desired Transfer Codes 185
7.4.1 Synthesis of Transfer Code: D²/(D² . 3D + 2) 186
7.4.1.1 Synthesizing with Buck-Boost Converter 187
7.4.1.2 Synthesizing with Zeta Converter 188
7.4.1.3 Synthesizing with uk Converter 189
7.4.2 Synthesizing Converters with the Fundamentals 191
7.4.2.1 DC Voltage and DC Current Offsetting 191
7.4.2.2 Inductor and Capacitor Splitting 192
7.4.2.3 DC Voltage Blocking and Filtering 192
7.4.2.4 Magnetic Coupling 193
7.4.2.5 DC Transformer 194
7.4.2.6 Switch and Diode Grafting 195
7.4.2.7 Layer Technique 195
Further Reading 198
8 Synthesis of Multistage and Multilevel Converters 199
8.1 Review of the Original Converter and Its Variations of Transfer Code 199
8.2 Syntheses of Single-Phase Converters 201
8.3 Syntheses of Three-Phase Converters 203
8.4 Syntheses of Multilevel Converters 207
8.5 L-C Networks 210
Further Reading 212
9 Synthesis of Soft-Switching PWM Converters 215
9.1 Soft-Switching Cells 215
9.1.1 Passive Lossless Soft-Switching Cells 216
9.1.1.1 Near-Zero-Current Switching Mechanism 216
9.1.1.2 Near-Zero-Voltage Switching Mechanism 218
9.1.2 Active Lossless Soft-Switching Cells 220
9.1.2.1 Zero-Voltage Switching Mechanism 222
9.1.2.2 Zero-Current Switching Mechanism 226
9.2 Synthesis of Soft-Switching PWM Converters with Graft Scheme 230
9.2.1 Generation of Passive Soft-Switching PWM Converters 230
9.2.2 Generation of Active Soft-Switching PWM Converters 234
9.3 Synthesis of Soft-Switching PWM Converters with Layer Scheme 240
9.3.1 Generation of Passive Soft-Switching PWM Converters 240
9.3.2 Generation of Active Soft-Switching PWM Converters 245
9.4 Discussion 247
Further Reading 251
10 Determination of Switch-Voltage Stresses 255
10.1 Switch-Voltage Stress of the Original Converter 255
10.2 Switch-Voltage Stresses of the Fundamental Converters 257
10.2.1 The Six Well-Known PWM Converters 257
10.2.1.1 Boost Converter 257
10.2.1.2 Buck-Boost Converter 258
10.2.1.3 uk, Sepic, and Zeta Converters 259
10.2.2 z-Source Converters 260
10.2.2.1 Voltage-Fed z-Source Converter 260
10.2.2.2 Current-Fed z-Source Converter 261
10.2.2.3 Quasi-z-Source Converter 262
10.3 Switch-Voltage Stresses of Non-Fundamental Converters 263
10.3.1 High Step-Down Switched-Inductor Converter 263
10.3.2 High Step-Down/Step-Up Switched-Inductor Converter 264
10.3.3 Compound Step-Down/Step-Up Switched-Capacitor Converter 265
10.3.4 High Step-Down Converter with Transfer Ratio of D² 267
10.3.5 High Step-Up Converter with Transfer Ratio of 1/(1 . D)² 268
Further Reading 270
11 Discussion and Conclusion 271
11.1 Will Identical Transfer Code Yield the Same Converter Topology? 271
11.2 Topological Duality Versus Circuital Duality 274
11.3 Graft and Layer Schemes for Synthesizing New Fundamental Converters 277
11.3.1 Synthesis of Buck-Boost Converter 278
11.3.2 Synthesis of Boost-Buck (uk) Converter 279
11.3.3 Synthesis of Buck-Boost-Buck (Zeta) Converter 280
11.3.4 Synthesis of Boost-Buck-Boost (Sepic) Converter 282
11.3.5 Synthesis of Buck-Family Converters with Layer Scheme 284
11.3.6 Synthesis of Boost-Family Converters with Layer Scheme 286
11.4 Analogy of Power Converters to DNA 289
11.4.1 Replication 291
11.4.2 Mutation 291
11.5 Conclusions 295
Further Reading 296
Part II Modeling and Application 299
12 Modeling of PWM DC/DC Converters 301
12.1 Generic Modeling of the Original Converter 302
12.2 Series-Shunt and Shunt-Series Pairs 303
12.3 Two-Port Network 308
12.4 Small-Signal Modeling of the Converters Based on Layer Scheme 315
12.5 Quasi-Resonant Converters 323
Further Reading 326
13 Modeling of PWM DC/DC Converters Using the Graft Scheme 329
13.1 Cascade Family 330
13.2 Small-Signal Models of Buck-Boost and uk Converters Operated in CCM 332
13.2.1 Buck-Boost Converter 336
13.2.2 Boost-Buck Converter 338
13.3 Small-Signal Models of Zeta and Sepic Operated in CCM 340
13.3.1 Zeta Converter 344
13.3.2 Sepic Converter 346
Further Reading 349
14 Modeling of Isolated Single-Stage Converters with High Power Factor and Fast Regulation 351
14.1 Generation of Single-Stage Converters with High Power Factor and Fast Regulation 352
14.2 Small-Signal Models of General Converter Forms Operated in CCM/DCM 355
14.3 An Illustration Example 361
Further Reading 365
15 Analysis and Design of an Isolated Single-Stage Converter Achieving Power Factor Correction and Fast Regulation 367
15.1 Derivation of the Single-Stage Converter 368
15.1.1 Selection of Individual Semi-Stages 369
15.1.2 Derivation of the Discussed Isolated Single-Stage Converter 369
15.2 Analysis of the Isolated Single-Stage Converter Operated in DCM + DCM 369
15.2.1 Buck-Boost Power Factor Corrector 370
15.2.2 Flyback Regulator 372
15.3 Design of a Peak Current Mode Controller for the ISSC 373
15.4 Practical Consideration and Design Procedure 377
15.4.1 Component Stress 377
15.4.2 Snubber Circuit 378
15.4.3 Design Procedure 379
15.5 Hardware Measurements 380
15.6 Design of an H¯ infinity Robust Controller for the ISSC 382
15.6.1 H¯ infinity Control 382
15.6.2 An Illustration Example of Robust Control and Hardware Measurements 386
Further Reading 392
Index 395
Acknowledgments xvii
About the Authors xviii
Part I Decoding and Synthesizing 1
1 Introduction 3
1.1 Power Processing Systems 4
1.2 Non-PWM Converters Versus PWM Converters 7
1.2.1 Non-PWM Converters 7
1.2.2 PWM Power Converters 9
1.3 Well-Known PWM Converters 10
1.4 Approaches to Converter Development 17
1.5 Evolution 25
1.6 About the Text 26
1.6.1 Part I: Decoding and Synthesizing 26
1.6.2 Part II: Modeling and Applications 28
Further Reading 28
2 Discovery of Original Converter 31
2.1 Creation of Original Converter 31
2.1.1 Source-Load Approach 32
2.1.2 Proton-Neutron-Meson Analogy 32
2.1.3 Resonance Approach 33
2.2 Fundamental PWM Converters 34
2.2.1 Voltage Transfer Ratios 35
2.2.2 CCM Operation 36
2.2.3 DCM Operation 38
2.2.4 Inverse Operation 39
2.3 Duality 40
Further Reading 41
3 Fundamentals 43
3.1 DC Voltage and Current Offsetting 43
3.1.1 DC Voltage Offsetting 44
3.1.2 DC Current Offsetting 47
3.2 Capacitor and Inductor Splitting 49
3.3 DC-Voltage Blocking and Pulsating-Voltage Filtering 51
3.4 Magnetic Coupling 55
3.5 DC Transformer 58
3.6 Switch Grafting 62
3.7 Diode Grafting 67
3.8 Layer Scheme 72
Further Reading 74
4 Decoding Process 77
4.1 Transfer Ratios (Codes) 77
4.2 Transfer Code Configurations 82
4.2.1 Cascade Configuration 82
4.2.2 Feedback Configuration 82
4.2.3 Feedforward Configuration 83
4.2.4 Parallel Configuration 85
4.3 Decoding Approaches 86
4.3.1 Factorization 86
4.3.2 Long Division 88
4.3.3 Cross Multiplication 89
4.4 Decoding of Transfer Codes with Multivariables 91
4.5 Decoding with Component-Interconnected Expression 93
Further Reading 94
5 Synthesizing Process with Graft Scheme 95
5.1 Cell Approaches 95
5.1.1 P-Cell and N-Cell 96
5.1.2 Tee Canonical Cell and Pi Canonical Cell 97
5.1.3 Switched-Capacitor Cell and Switched-Inductor Cell 98
5.1.4 Inductor-Capacitor Component Cells 100
5.2 Converter Grafting Scheme 101
5.2.1 Synchronous Switch Operation 101
5.2.2 Grafting Active Switches 103
5.2.3 Grafting Passive Switches 108
5.3 Illustration of Grafting Converters 110
5.3.1 Grafting the Well-Known PWM Converters 110
5.3.1.1 Graft Boost on Buck 111
5.3.1.2 Graft Buck on Boost 112
5.3.1.3 Graft Buck on Buck-Boost 114
5.3.1.4 Graft Boost on Boost-Buck 116
5.3.1.5 Buck in Parallel with Buck-Boost 119
5.3.1.6 Grafting Buck on Buck to Achieve High Step-Down Voltage Conversion 119
5.3.1.7 Grafting Boost on Boost to Achieve High Step-up Voltage Conversion 120
5.3.1.8 Grafting Boost (CCM) on Buck (DCM) 121
5.3.1.9 Cascode Complementary Zeta with Buck 123
5.3.2 Grafting Various Types of Converters 124
5.3.2.1 Grafting Half-Bridge Resonant Inverter on Dither Boost Converter 124
5.3.2.2 Grafting Half-Bridge Resonant Inverter on Bidirectional Flyback Converter 124
5.3.2.3 Grafting Class-E Converter on Boost Converter 125
5.3.3 Integrating Converters with Active and Passive Grafted Switches 127
5.3.3.1 Grafting Buck on Boost with Grafted Diode 128
5.3.3.2 Grafting Half-Bridge Inverter on Interleaved Boost Converters in DCM 128
5.3.3.3 Grafting N-Converters with TGS 130
5.3.3.4 Grafting N-Converters with PiGS 130
Further Reading 132
6 Synthesizing Process with Layer Scheme 133
6.1 Converter Layering Scheme 133
6.2 Illustration of Layering Converters 135
6.2.1 Buck Family 135
6.2.2 Boost Family 138
6.2.3 Other Converter Examples 142
6.3 Discussion 146
6.3.1 Deduction from uk to Buck-Boost 146
6.3.2 Deduction from Sepic to Buck-Boost 148
6.3.3 Deduction from Zeta to Buck-Boost 149
6.3.4 Deduction from Sepic to Zeta 150
Further Reading 151
7 Converter Derivation with the Fundamentals 153
7.1 Derivation of Buck Converter 153
7.1.1 Synthesizing with Buck-Boost Converter 154
7.1.2 Synthesizing with uk Converter 154
7.2 Derivation of z-Source Converters 154
7.2.1 Voltage-Fed z-Source Converters 155
7.2.1.1 Synthesizing with Sepic Converter 157
7.2.1.2 Synthesizing with Zeta Converter 160
7.2.2 Current-Fed z-Source Converters 161
7.2.2.1 Synthesizing with SEPIC Converter 162
7.2.2.2 Synthesizing with Zeta Converter 162
7.2.3 Quasi-z-Source Converter 162
7.2.3.1 Synthesizing with Sepic Converter 164
7.2.3.2 Synthesizing with Zeta Converter 165
7.3 Derivation of Converters with Switched Inductor or Switched Capacitor 166
7.3.1 Switched-Inductor Converters 167
7.3.1.1 High Step-Down Converter with Transfer Code D/(2 . D) 167
7.3.1.2 High Step-Down Converter with Transfer Code D/(2(1 . D)) 173
7.3.2 Switched-Capacitor Converters 178
7.3.2.1 High Step-Up Converter with Transfer Code (1 + D)/(1 . D) 178
7.3.2.2 High Step-Up Converter with Transfer Code 2D/(1 . D) 181
7.3.2.3 High Step-Up Converter with Transfer Code D/(1 . 2D) 184
7.4 Syntheses of Desired Transfer Codes 185
7.4.1 Synthesis of Transfer Code: D²/(D² . 3D + 2) 186
7.4.1.1 Synthesizing with Buck-Boost Converter 187
7.4.1.2 Synthesizing with Zeta Converter 188
7.4.1.3 Synthesizing with uk Converter 189
7.4.2 Synthesizing Converters with the Fundamentals 191
7.4.2.1 DC Voltage and DC Current Offsetting 191
7.4.2.2 Inductor and Capacitor Splitting 192
7.4.2.3 DC Voltage Blocking and Filtering 192
7.4.2.4 Magnetic Coupling 193
7.4.2.5 DC Transformer 194
7.4.2.6 Switch and Diode Grafting 195
7.4.2.7 Layer Technique 195
Further Reading 198
8 Synthesis of Multistage and Multilevel Converters 199
8.1 Review of the Original Converter and Its Variations of Transfer Code 199
8.2 Syntheses of Single-Phase Converters 201
8.3 Syntheses of Three-Phase Converters 203
8.4 Syntheses of Multilevel Converters 207
8.5 L-C Networks 210
Further Reading 212
9 Synthesis of Soft-Switching PWM Converters 215
9.1 Soft-Switching Cells 215
9.1.1 Passive Lossless Soft-Switching Cells 216
9.1.1.1 Near-Zero-Current Switching Mechanism 216
9.1.1.2 Near-Zero-Voltage Switching Mechanism 218
9.1.2 Active Lossless Soft-Switching Cells 220
9.1.2.1 Zero-Voltage Switching Mechanism 222
9.1.2.2 Zero-Current Switching Mechanism 226
9.2 Synthesis of Soft-Switching PWM Converters with Graft Scheme 230
9.2.1 Generation of Passive Soft-Switching PWM Converters 230
9.2.2 Generation of Active Soft-Switching PWM Converters 234
9.3 Synthesis of Soft-Switching PWM Converters with Layer Scheme 240
9.3.1 Generation of Passive Soft-Switching PWM Converters 240
9.3.2 Generation of Active Soft-Switching PWM Converters 245
9.4 Discussion 247
Further Reading 251
10 Determination of Switch-Voltage Stresses 255
10.1 Switch-Voltage Stress of the Original Converter 255
10.2 Switch-Voltage Stresses of the Fundamental Converters 257
10.2.1 The Six Well-Known PWM Converters 257
10.2.1.1 Boost Converter 257
10.2.1.2 Buck-Boost Converter 258
10.2.1.3 uk, Sepic, and Zeta Converters 259
10.2.2 z-Source Converters 260
10.2.2.1 Voltage-Fed z-Source Converter 260
10.2.2.2 Current-Fed z-Source Converter 261
10.2.2.3 Quasi-z-Source Converter 262
10.3 Switch-Voltage Stresses of Non-Fundamental Converters 263
10.3.1 High Step-Down Switched-Inductor Converter 263
10.3.2 High Step-Down/Step-Up Switched-Inductor Converter 264
10.3.3 Compound Step-Down/Step-Up Switched-Capacitor Converter 265
10.3.4 High Step-Down Converter with Transfer Ratio of D² 267
10.3.5 High Step-Up Converter with Transfer Ratio of 1/(1 . D)² 268
Further Reading 270
11 Discussion and Conclusion 271
11.1 Will Identical Transfer Code Yield the Same Converter Topology? 271
11.2 Topological Duality Versus Circuital Duality 274
11.3 Graft and Layer Schemes for Synthesizing New Fundamental Converters 277
11.3.1 Synthesis of Buck-Boost Converter 278
11.3.2 Synthesis of Boost-Buck (uk) Converter 279
11.3.3 Synthesis of Buck-Boost-Buck (Zeta) Converter 280
11.3.4 Synthesis of Boost-Buck-Boost (Sepic) Converter 282
11.3.5 Synthesis of Buck-Family Converters with Layer Scheme 284
11.3.6 Synthesis of Boost-Family Converters with Layer Scheme 286
11.4 Analogy of Power Converters to DNA 289
11.4.1 Replication 291
11.4.2 Mutation 291
11.5 Conclusions 295
Further Reading 296
Part II Modeling and Application 299
12 Modeling of PWM DC/DC Converters 301
12.1 Generic Modeling of the Original Converter 302
12.2 Series-Shunt and Shunt-Series Pairs 303
12.3 Two-Port Network 308
12.4 Small-Signal Modeling of the Converters Based on Layer Scheme 315
12.5 Quasi-Resonant Converters 323
Further Reading 326
13 Modeling of PWM DC/DC Converters Using the Graft Scheme 329
13.1 Cascade Family 330
13.2 Small-Signal Models of Buck-Boost and uk Converters Operated in CCM 332
13.2.1 Buck-Boost Converter 336
13.2.2 Boost-Buck Converter 338
13.3 Small-Signal Models of Zeta and Sepic Operated in CCM 340
13.3.1 Zeta Converter 344
13.3.2 Sepic Converter 346
Further Reading 349
14 Modeling of Isolated Single-Stage Converters with High Power Factor and Fast Regulation 351
14.1 Generation of Single-Stage Converters with High Power Factor and Fast Regulation 352
14.2 Small-Signal Models of General Converter Forms Operated in CCM/DCM 355
14.3 An Illustration Example 361
Further Reading 365
15 Analysis and Design of an Isolated Single-Stage Converter Achieving Power Factor Correction and Fast Regulation 367
15.1 Derivation of the Single-Stage Converter 368
15.1.1 Selection of Individual Semi-Stages 369
15.1.2 Derivation of the Discussed Isolated Single-Stage Converter 369
15.2 Analysis of the Isolated Single-Stage Converter Operated in DCM + DCM 369
15.2.1 Buck-Boost Power Factor Corrector 370
15.2.2 Flyback Regulator 372
15.3 Design of a Peak Current Mode Controller for the ISSC 373
15.4 Practical Consideration and Design Procedure 377
15.4.1 Component Stress 377
15.4.2 Snubber Circuit 378
15.4.3 Design Procedure 379
15.5 Hardware Measurements 380
15.6 Design of an H¯ infinity Robust Controller for the ISSC 382
15.6.1 H¯ infinity Control 382
15.6.2 An Illustration Example of Robust Control and Hardware Measurements 386
Further Reading 392
Index 395
Tsai-Fu Wu, PhD, is a Distinguished Professor in the Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan. Dr. Wu has been an Associate Editor for the IEEE Transactions on Power Electronics since 2000.
Yu-Kai Chen, PhD, is a Professor in the Innovative Design and Energy Application Laboratory at National Formosa University, Yunlin, Taiwan.
Yu-Kai Chen, PhD, is a Professor in the Innovative Design and Energy Application Laboratory at National Formosa University, Yunlin, Taiwan.
