1. Auflage - November 2008
91,90 Euro
2008. 386 Seiten, Hardcover
- Praktikerbuch -
ISBN-10: 0-470-11280-8
ISBN-13: 978-0-470-11280-9 - John Wiley & Sons

Preis inkl. Mehrwertsteuer zzgl. Versandkosten.





Probekapitel

Kurzbeschreibung
The current semiconductor model continues to give birth to a large number of design engineers who are producing a large number of chips, but without any interaction with process/device people. This book addresses major challenges faced by engineers and offers concrete solutions provided by industry experts. This book serves as a practical, yet highly advanced, tutorial for engineers and students who want to be more familiar with design issues associated with Nano-CMOS process technologies.

Aus dem Inhalt
1. Introduction.

1.1 DFM - Value proposition.

1.2 Deficiencies in Boolean-based Design Rules in the sub-wavelength regime [6].

1.3 Impact of Variability on Yield and Performance.

1.4 The industry challenge - disappearing process window.

1.5 Mobility enhancement techniques - a new source of variability induced by design process interaction.

1.6 Design dependency of chip surface topology.

1.7 Newly exacerbated narrow width effect in nano-CMOS nodes.

1.8 Well proximity effect.

1.9 Scaling beyond 65nm drives the need for model based DFM solutions.

1.10 Summary.

PART 1: NEWLY EXACERBATED EFFECTS.

2. Lithography related Aspects of DFM.

2.1 Economic motivations for DFM.

2.2 Lithographic tools and techniques for advanced technology nodes.

2.3 Lithography limited yield.

2.4 Lithography driven DFM Solutions.

3. Interaction of layout with transistor performance and stress engineering techniques.

3.1 Introduction.

3.2 Impact of stress on transistor performance.

3.3 Stress propagation.

3.4 Stress sources.

3.5 Introducing stress into transistors.

PART 2: DESIGN SOLUTIONS.

4. Signal and Power Integrity.

4.1 Introduction.

4.2 Interconnect Resistance, Capacitance and Inductance.

4.3 Inductance Effects on Interconnect.

5. Analog and Mixed Signal Circuit Design for Yield and Manufacturability.

5.1 Introduction.

5.2 Guidelines.

5.3 Device Selection.

5.4 Device Size Heart Beat.

5.5 Device Matching.

5.6 Design Guidelines.

5.7 Layout Guidelines.

5.8 Test.

6. Design for Variability, Performance and Yield.

6.1 Introduction.

6.2 Impact of variations (introduced by both process and circuit operation) on the design.

6.3 Some Parametric Fluctuations with new implications for design .

6.4 Process Variations in Interconnects.

6.5 Impact of Deep Sub-Micron Integration in SRAMs.

6.6 Impact of Layout Styles on Manufacturability, Yield and Scalability.

6.7 Design for variations.

6.8 Summary.

PART 3: THE ROAD TO DFM.

7. Nano-CMOS design tools: Beyond model-based analysis and correction.

7.1 Introduction.

7.2 Electrical Design for Manufacturability (DFM).

7.3 Criticality Aware DFM.

7.4 On Guardbands, Statistics, and Gaps.

7.5 Opportunistic Mindsets.

7.6 Futures at ó 45nm .

7.7 Summary.

7.8 References.