Integrated Circuit Failure Analysis
A Guide to Preparation Techniques
Wiley Series in Quality and Reliability Engineering
Januar 1998
190 Seiten, Hardcover
Wiley & Sons Ltd
Kurzbeschreibung
Funktionstests an integrierten Schaltungen sind für deren Zuverlässigkeit von herausragender Bedeutung. Erstmals werden in diesem Werk die speziellen Präparationstechniken für die Fehleranalyse beschrieben. Ausgehend von den theoretischen Grundlagen erläutert der Autor in praxisnahem Stil die verschiedenen Techniken, die das Zurückverfolgen von Ausfällen ermöglichen.
Fault analysis of highly-integrated semiconductor circuits has become an indispensable discipline in the optimization of product quality. Integrated Circuit Failure Analysis describes state-of-the-art procedures for exposing suspected failure sites in semiconductor devices. The author adopts a hands-on problem-oriented approach, founded on many years of practical experience, complemented by the explanation of basic theoretical principles. Features include: Advanced methods in device preparation and technical procedures for package inspection and semiconductor reliability. Illustration of chip isolation and step-by-step delayering of chips by wet chemical and modern plasma dry etching techniques. Particular analysis of bipolar and MOS circuits, although techniques are equally relevant to other semiconductors. Advice on the choice of suitable laboratory equipment. Numerous photographs and drawings providing guidance for checking results. Focusing on modern techniques, this practical text will enable both academic and industrial researchers and IC designers to expand the range of analytical and preparative methods at their disposal and to adapt to the needs of new technologies.
Introduction; Package Decapsulation; Isolation of the Chip; Wet-chemical Etching Procedures for Removing Chip Layers; Crystallographic Etching of the Silicon Substrate; Dry Etching in Plasma; Cross-sectioning Methods; Metallography; Outlook; Index; Appendix.
