John Wiley & Sons Digital VLSI Design and Simulation with Verilog Cover Master digital design with VLSI and Verilog using this up-to-date and comprehensive resource from le.. Product #: 978-1-119-77804-2 Regular price: $107.48 $107.48 Auf Lager

Digital VLSI Design and Simulation with Verilog

Lata Tripathi, Suman / Saxena, Sobhit / Sinha, Sanjeet K. / Patel, Govind S

Cover

1. Auflage Januar 2022
224 Seiten, Hardcover
Wiley & Sons Ltd

ISBN: 978-1-119-77804-2
John Wiley & Sons

Jetzt kaufen

Preis: 115,00 €

Preis inkl. MwSt, zzgl. Versand

Weitere Versionen

epubmobipdf

Master digital design with VLSI and Verilog using this up-to-date and comprehensive resource from leaders in the field

Digital VLSI Design Problems and Solution with Verilog delivers an expertly crafted treatment of the fundamental concepts of digital design and digital design verification with Verilog HDL. The book includes the foundational knowledge that is crucial for beginners to grasp, along with more advanced coverage suitable for research students working in the area of VLSI design. Including digital design information from the switch level to FPGA-based implementation using hardware description language (HDL), the distinguished authors have created a one-stop resource for anyone in the field of VLSI design.

Through eleven insightful chapters, you?ll learn the concepts behind digital circuit design, including combinational and sequential circuit design fundamentals based on Boolean algebra. You?ll also discover comprehensive treatments of topics like logic functionality of complex digital circuits with Verilog, using software simulators like ISim of Xilinx. The distinguished authors have included additional topics as well, like:
* A discussion of programming techniques in Verilog, including gate level modeling, model instantiation, dataflow modeling, and behavioral modeling
* A treatment of programmable and reconfigurable devices, including logic synthesis, introduction of PLDs, and the basics of FPGA architecture
* An introduction to System Verilog, including its distinct features and a comparison of Verilog with System Verilog
* A project based on Verilog HDLs, with real-time examples implemented using Verilog code on an FPGA board

Perfect for undergraduate and graduate students in electronics engineering and computer science engineering, Digital VLSI Design Problems and Solution with Verilogalso has a place on the bookshelves of academic researchers and private industry professionals in these fields.

Suman Lata Tripathi is Professor of VLSI Design at Lovely Professional University, India. She is a senior member of the IEEE and received her PhD in microelectronics and VLSI Design from Motilal Nehru National Institute of Technology, Allahabad, India.

Sobhit Saxena is Associate Professor of VLSI Design at Lovely Professional University, India. He received his PhD from IIT Roorkee, India.

Sanjeet K. Sinha, PhD, is Associate Professor of VLSI Design at Lovely Professional University, India. He received his PhD from the National Institute of Technology, Silchar, India.

Govind S. Patel, PhD, is Professor of VLSI Design at IIMT College of Engineering, Greater Noida, UP, India. He received his doctorate from Thapar University in Patiala, India.