ESD
Analog Circuits and Design
1. Auflage Oktober 2014
296 Seiten, Hardcover
Wiley & Sons Ltd
Kurzbeschreibung
A comprehensive and in-depth review of the field, ESD: Analog Circuits and Design provides a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design. Written for electrical engineers and students, this accessible text focuses on circuit and circuit design applications, describing analog design fundamentals (circuit fundamentals) as well as the various ESD implications. The text covers a large breadth of subjects and technologies, such as CMOS, LDMOS, BCD, SOI, and thick body SOI.
A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design
This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design. It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect presents the additional challenges associated with the design of adequate and effective ESD protection elements and schemes. A comprehensive list of practical application examples is used to demonstrate the successful combination of both techniques and any potential design trade-offs.
Chapter One looks at analog design discipline, including layout and analog matching and analog layout design practices. Chapter Two discusses analog design with circuits, examining: single transistor amplifiers; multi-transistor amplifiers; active loads and more. The third chapter covers analog design layout (also MOSFET layout), before Chapters Four and Five discuss analog design synthesis. The next chapters introduce the reader to analog-digital mixed signal design synthesis, analog signal pin ESD networks, and analog ESD power clamps. Chapter Nine, the last chapter, covers ESD design in analog applications.
* Clearly describes analog design fundamentals (circuit fundamentals) as well as outlining the various ESD implications
* Covers a large breadth of subjects and technologies, such as CMOS, LDMOS, BCD, SOI, and thick body SOI
* Establishes an "ESD analog design" discipline that distinguishes itself from the alternative ESD digital design focus
* Focuses on circuit and circuit design applications
* Assessible, with the artwork and tutorial style of the ESD book series
* PowerPoint slides are available for university faculty members
Even in the world of digital circuits, analog and power circuits are two very important but under-addressed topics, especially from the ESD aspect. Dr. Voldman's new book will serve as an essential and practical guide to the greater IC community. With high practical and academic values this book is a "bible" for professionals, graduate students, device and circuit designers for investigating the physics of ESD and for product designs and testing.
Preface xix
Acknowledgments xxiii
1 Analog, ESD, and EOS 1
1.1 ESD in Analog Design 1
1.2 Analog Design Discipline and ESD Circuit Techniques 2
1.3 Design Symmetry and ESD 5
1.4 ESD Design Synthesis and Architecture Flow 6
1.5 ESD Design and Noise 7
1.6 ESD Design Concepts: Adjacency 8
1.7 Electrical Overstress 8
1.8 Reliability Technology Scaling and the Reliability Bathtub Curve 13
1.9 Safe Operating Area 15
1.10 Closing Comments and Summary 17
References 18
2 Analog Design Layout 19
2.1 Analog Design Layout Revisited 19
2.2 Common Centroid Design 22
2.3 Interdigitation Design 24
2.4 Common Centroid and Interdigitation Design 24
2.5 Passive Element Design 25
2.6 Resistor Element Design 25
2.7 Capacitor Element Design 29
2.8 Inductor Element Design 30
2.9 Diode Design 33
2.10 MOSFET Design 35
2.11 Bipolar Transistor Design 36
2.12 Closing Comments and Summary 36
References 37
3 Analog Design Circuits 39
3.1 Analog Circuits 39
3.2 Single-Ended Receivers 40
3.3 Differential Receivers 41
3.4 Comparators 43
3.5 Current Sources 43
3.6 Current Mirrors 44
3.7 Voltage Regulators 46
3.8 Voltage Reference Circuits 49
3.9 Converters 49
3.10 Oscillators 50
3.11 Phase Lock Loop 50
3.12 Delay Locked Loop 50
3.13 Closing Comments and Summary 52
References 52
4 Analog ESD Circuits 55
4.1 Analog ESD Devices and Circuits 55
4.2 ESD Diodes 55
4.3 ESD MOSFET Circuits 59
4.4 ESD Silicon-Controlled Rectifier Circuits 62
4.5 Laterally Diffused MOS Circuits 64
4.6 DeMOS Circuits 68
4.7 Ultrahigh-Voltage LDMOS Circuits 69
4.8 Closing Comments and Summary 72
References 72
5 Analog and ESD Design Synthesis 73
5.1 Early ESD Failures in Analog Design 73
5.2 Mixed-Voltage Interface: Voltage Regulator Failures 73
5.3 Separation of Analog Power from Digital Power AVDD to DVDD 76
5.4 ESD Failure in Phase Lock Loop (PLL) and System Clock 77
5.5 ESD Failure in Current Mirrors 77
5.6 ESD Failure in Schmitt Trigger Receivers 78
5.7 Isolated Digital and Analog Domains 82
5.8 ESD Protection Solution: Connectivity of AVDD to VDD 82
5.9 Connectivity of AVSS to DVSS 83
5.10 Digital and Analog Domain with ESD Power Clamps 84
5.11 Digital and Analog Domain with Master/Slave ESD Power Clamps 86
5.12 High-Voltage, Digital, and Analog Domain Floor Plan 87
5.13 Closing Comments and Summary 88
References 88
6 Analog-to-Digital ESD Design Synthesis 89
6.1 Digital and Analog 89
6.2 Interdomain Signal Line ESD Failures 90
6.3 Digital-to-Analog Core Spatial Isolation 92
6.4 Digital-to-Analog Core Ground Coupling 92
6.5 Domain-to-Domain Signal Line ESD Networks 94
6.6 Domain-to-Domain Third-Party Coupling Networks 94
6.7 Domain-to-Domain Cross-Domain ESD Power Clamp 95
6.8 Digital-to-Analog Domain Moat 96
6.9 Digital-to-Analog Domain Moat with Through-Silicon Via 96
6.10 Domain-to-Domain ESD Design Rule Check and Verification Methods 97
6.11 Closing Comments and Summary 97
References 97
7 Analog-ESD Signal Pin Co-synthesis 101
7.1 Analog Signal Pin 101
7.2 Analog Signal Differential Receiver 102
7.3 Analog CMOS Differential Receiver 108
7.4 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout 110
7.5 Analog Differential Pair Common Centroid Design Layout: Signal Pin-to-Signal Pin and Parasitic ESD Elements 113
7.6 Closing Comments and Summary 115
References 116
8 Analog and ESD Circuit Integration 119
8.1 Analog and Power Technology and ESD Circuit Integration 119
8.2 ESD Input Circuits 120
8.3 Analog ESD Output Circuits 123
8.4 Analog ESD Ground-to-Ground Networks 124
8.5 ESD Power Clamps 125
8.6 ESD Power Clamps for Low-Voltage Digital and Analog Domain 129
8.7 ESD Power Clamp Issues 137
8.8 ESD Power Clamp Design 138
8.9 Bipolar ESD Power Clamps 144
8.10 Closing Comments and Summary 145
References 146
9 System-Level EOS Issues for Analog Design 147
9.1 EOS Protection Devices 147
9.2 EOS Protection Device: Directionality 150
9.3 System-Level Pulse Model 152
9.4 EOS Transient Voltage Suppression (TVS) 155
9.5 EOS Current Suppression Devices 161
9.6 EOS and EMI Prevention: Printed Circuit Board Design 166
9.7 Closing Comments and Summary 171
References 171
10 Latchup Issues for Analog Design 173
10.1 Latchup in Analog Applications 173
10.2 I/O-to-I/O Latchup 173
10.3 I/O-to-I/O Latchup: N-Well to N-Well 175
10.4 I/O-to-I/O Latchup: N-Well to NFET 177
10.5 I/O-to-I/O Latchup: NFET to NFET 179
10.6 I/O-to-I/O Latchup: N-Well Guard Ring between Adjacent Cells 180
10.7 Latchup of Analog I/O to Adjacent Structures 181
10.8 Analog I/O to Core 182
10.9 Core-to-Core Analog-Digital Floor Planning 182
10.10 High-Voltage Guard Rings 184
10.11 Through-Silicon Via (TSV) 185
10.12 Trench Guard Rings 186
10.13 Active Guard Rings 187
10.14 Closing Comments and Summary 190
References 191
11 Analog ESD Library and Documents 195
11.1 Analog Design Library 195
11.2 Analog Device Library: Passive Elements 195
11.3 Analog Device Library: Active Elements 197
11.4 Analog Design Library: Repository of Analog Circuits and Cores 198
11.5 ESD Device Library 198
11.6 Cadence-Based Parameterized Cells (PCells) 199
11.7 Analog ESD Documents 208
11.8 ESD Cookbook 212
11.9 Electrical Overstress (EOS) Documents 213
11.10 Closing Comments and Summary 220
References 220
12 Analog ESD and Latchup Design Rule Checking and Verification 223
12.1 Electronic Design Automation 223
12.2 Electrical Overstress (EOS) and ESD Design Rule Checking 223
12.3 Electrical Overstress (EOS) Electronic Design Automation 227
12.4 Printed Circuit Board (PCB) Design Rule Checking and Verification 230
12.5 Electrical Overstress and Latchup Design Rule Checking (DRC) 232
12.6 Whole-Chip Checking and Verification Methods 240
12.7 Cross-Domain Signal Line Checking and Verification 241
12.8 Closing Comments and Summary 246
References 246
Appendix: Standards 251
Appendix: Glossary of Terms 255
Index 261